• Minister of State for Electronics and Information Technology Rajeev Chandrasekar virtually addressed the Digital India RISC-V (DIR-V) Symposium organised by IIT Madras.

• The minister emphasized the government’s vision for DIR-V with effective public-private partnerships and collaborations with premiere academic institutions.

• He said the government of India is fully committed to making DIR-V the Indian ISA (Instruction Set Architecture).

RISC-V project

• RISC stands for ‘Reduced Instruction Set Computer’ and ‘V’ stands for fifth generation. 

• The RISC-V project commenced in 2010 and it aims to deliver a new level of free extensible software (software that allows new functionality and capability additions) and hardware freedom on architecture. 

• The RISC-V ISA enables a new era of processor innovation through open standard collaboration and aims to deliver a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. 

• IIT-Madras professor V. Kamakoti designed India’s first indigenously-developed microprocessor ‘SHAKTI’ on RISC-V ISA.

• The RISC-V foundation was formed in 2015 with IIT Madras being one of the founder members.

• The RISC-V ISA based designs are used by many companies and startups. 

• It is open source and free of cost. For academicians, the pedagogy of RISC-V ISA opens up an industry-relevant curriculum with numerous exciting research and applications.

• The Digital India RISC-V (DIR-V) microprocessor programme was launched in 2022 with the aim of developing a portfolio of RISC-V based microprocessors.

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